1. Field of the Invention
The present invention generally relates t non-volatile semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device (hereinafter referred to as a flash memory) which is capable of electrical programming and erasing of data and employs a floating gate.
2. Description of the Background Art
FIG. 4 is a cross sectional view showing a conventional flash memory.
This memory cell has two gate electrodes; a floating gate 3 completely covered with a silicon oxide film and a control gate 4 stacked thereon. A tunnel oxide film 2 which is a thin (80-100 .ANG.) oxide film is provided between floating gate 3 and a semiconductor substrate 1. For writing or erasing of the data, electrons are introduced to or emitted from floating gate 3 by a current flowing through tunnel oxide film 2 (a tunnel current).
A threshold voltage of a transistor (a gate voltage obtained when a drain current starts to flow) is changed by whether electrons are present in floating gate 3 or not. Since the drain current changes by the change in the threshold, "0" and "1" are distinguished from each other by the amount of the drain current. Such a memory cell is called a non-volatile memory cell because electrons remaining in floating gate 3 will not be lost even by turning off the power supply unless light is directed thereto. A kind of non-volatile memory which can write and erase data electrically is called a flash memory.
FIG. 5 is a cross sectional view of a flash memory showing only such a flash memory cell as described above and peripheral transistors. The flash memory basically includes a memory cell 6, a V.sub.CC type transistor 7 and a V.sub.PP type transistor 8. V.sub.CC type transistor 7 is a switching transistor for a supply voltage (V.sub.CC). V.sub.PP type transistor 8 is a programming transistor for applying a high voltage V.sub.PP to control gate 4.
Memory cell 6 includes tunnel oxide film 2, floating gate 3 and control gate 4, as described above. V.sub.CC type transistor 7 includes a first gate insulating film 9 and a first gate 10. V.sub.PP type transistor 8 includes a second gate insulating film 11 and a second gate 12. A conventional flash memory satisfies the following inequality: EQU t(TN)&lt;t(V.sub.CC)&lt;t(V.sub.PP) (1)
where t(TN) is a film thickness of tunnel oxide film 2, t(V.sub.CC) is a film thickness of first gate insulating film 9, and t(V.sub.PP) is a film thickness of second gate insulating film 11. In the conventional flash memory, a voltage of 5V is applied to V.sub.CC type transistor 7, and a voltage of 12V is applied to V.sub.PP type transistor 8.
Since flash memories are scaled down, there is a problem with a conventional flash memory structured in accordance with the inequality above. This problem will be described below in detail.
First, let us consider the electronic field applied to tunnel oxide film 2. Assuming that the amount of stored charges is approximately 10 fC/cell at present, when a scaling factor is k (k is a multiplier less than 1), the amount of stored charges will be k.times.10 fC/cell. In any generation, the charges must be extracted in approximately one second at most. Assuming that the area electrons pass through when charges are extracted is about 0.1 .mu.m.sup.2 (at present), this area will be k.times.0.1 .mu.m.sup.2 correspondingly (although the area might be k.sup.2 .times.0.1 .mu.m.sup.2 in some cases, it will not make any big difference to the discussion here). Therefore, a current density I (tunnel) of 10 .mu.A/cm.sup.2 must be ensured in any generation, as obtained from the following expression:
Current density I (tunnel)&gt;(k.times.10 fC)/(k.times.0.1 .mu.m.sup.2) .div.10 .mu.A/cm.sup.2
As long as charges are extracted by utilizing the Fowler-Nordheim tunnel phenomenon, current density J is obtained by the following expressions:
J (FN).div.AE.sup.2 exp (-B/E)
A=q.sup.2 m/8.pi.h.phi..sub.b m.sup.* .div.1.47.times.10.sup.-6 (A/V.sup.2)
B=-(4 (2m.sup.*).sup. 1/2 (q.phi..sub.b).sup. 3/2 /3qh).div.2.37.times.10.sup.10 (V/m)
where E is the electric field applied to an oxide film, q is elementary charges, m is the mass of an electron, h is the Planck's constant, .phi..sub.b is the barrier height against the oxide film, m.sup.* is the effective mass of an electron.
As can be seen from the expressions above, the electric field of at least 10 MV/cm must be ensured for the tunnel oxide film in any generation in order to obtain current density J of 10 .mu.A/cm.sup.2. Here, the electric field applied to the tunnel oxide film is defined as E(TN).
Although actually there are various methods of applying voltage to tunnel oxide film 2, it is assumed here for simplicity that a voltage of t(TN).times.E(TN) must be handled in chip where t(TN) is the film thickness of tunnel oxide film 2. In other words, a high voltage V.sub.PP in chip can be expressed by the following equation;
In-chip high voltage V.sub.PP =t(TN).times.E(TN)
Now, the film thickness of the gate oxide film of peripheral transistors handling the high voltage will be considered. Generally, when a voltage is applied to a silicon oxide film, the silicon oxide film will break down in a finite time. The life of a silicon oxide film is a function of the applied electric field and the area of the oxide film. (Although it is also related to the film thickness of the oxide film, it is not taken into consideration here because its effect is small.)
FIG. 6 shows the relationship between the life (sec) of a silicon oxide film and the applied electric field (Eg). As can be seen from FIG. 6, the life of a silicon oxide film is shortened as the applied voltage increases. From the figure, the electric field E(V.sub.PP) applied to the gate oxide film in a V.sub.PP type transistor must be less than 5 MV/cm so as to secure the life of ten years (.div.3.times.10.sup.8 second). Therefore, the expression of E(V.sub.PP)&lt;5 MV/cm must be satisfied.
Considering the effects of the area and the fact that V.sub.PP is not actually applied for as long as ten years, the expression of E(V.sub.PP)&lt;3-7 MV/cm must be satisfied.
From the consideration above, the film thickness t(V.sub.PP) of the gate oxide film in a V.sub.PP type transistor can be obtained from the following expressions: ##EQU1##
Therefore, if an oxide film having a thickness of 100 .ANG. is used as tunnel oxide film 2, the thickness of the gate oxide film in the V.sub.PP type transistor is suitably 150 .ANG.-330 .ANG..
Next, V.sub.CC type transistors will be considered. Regarding V.sub.CC type transistors as well, the life of ten years must be secured and, in that order, electric field E(V.sub.CC) applied to the gate insulating film in the V.sub.CC type transistor must be less than 3-5 MV/cm, as can be seen from FIG. 6. That is, E(V.sub.CC)&lt;3-5 MV/cm. Therefore, when V.sub.CC =5V, thickness t(V.sub.CC) of the gate oxide film in the V.sub.CC type transistor is 100 .ANG.-170 .ANG..
Since V.sub.CC of 5V is utilized in the conventional device, a flash memory satisfying the inequality (1) above has excelled in performance.
As long as reliability is secured, a transistor having a thinner gate oxide film enjoys the greater improvement in performance and thus is more advantageous in terms of performance of a chip such as access. Furthermore, it can be seen from the foregoing that if the voltage is scaled down, the thickness of the gate oxide film can be reduced in proportion thereto.
Meanwhile, regarding the scaling of the thickness of the tunnel oxide film, Naruke, et al. has pointed out a stress-induced leakage current at low electric field, which is the lower limit of the reliability (K. Naruke, et al., IEDM Tech. Dig., (1988) pp. 424).
Taking this point into consideration, scaling of the tunnel oxide film is said to be k.sup.0.25 (K. Yoshikawa, et al., Sympo. of VSLI Tech. Dig., (1991), pp. 79). According to Yoshikawa, et al., the thickness of the tunnel oxide film remains to be around 100 .ANG. even in the 64M (.about.0.4 .mu.m rule) generation.
Meantime, in order to achieve the best performance of the transistor with the given V.sub.CC as long as reliability is secured, the thickness of the transistor must be set as t(V.sub.CC)=V.sub.CC /E(V.sub.CC). This results in t(V.sub.CC) equal to 70 .ANG.-100 .ANG. in the generation where V.sub.CC =3.3V. Therefore, in the generation where V.sub.CC =3.3V, a conventional semiconductor device satisfying the expression (1) above cannot achieve a high reliability. More specifically, if the expression (1) above is to be satisfied, t(TN) must be less than 70 .ANG. because t(V.sub.CC)&gt;t(TN).
However, such a small amount of t(TN) gives rise to a problem of reliability, that is, a stress-induced leakage current at low electric field.